This remains a profoundly difficult undertaking. “The process of packaging isn’t as straightforward as simply declaring, ‘Our goal is to produce 100,000 wafers each month,'” explains Jim McGregor, a veteran semiconductor sector expert and the creator of Tirias Research, referencing the ongoing output of chips at different manufacturing phases. “Ultimately, the crucial factor is if Intel’s [packaging] fabrication facilities can secure agreements. Should we observe a greater expansion of these activities, it would signify their success.”
In the previous month, Anwar Ibrahim, Malaysia’s prime minister, disclosed via a Facebook update that Intel is enlarging its semiconductor production plants in Malaysia, initially set up during the 1970s. Ibrahim stated that Naga Chandrasekaran, who leads Intel’s Foundry division, had “delineated intentions to initiate the initial stage” of this growth, encompassing sophisticated packaging.
“I commend Intel’s choice to commence the complex’s operations later this year,” stated a translated rendition of Ibrahim’s social media entry. John Hipsher, an Intel representative, verified that the company is establishing extra chip assembly and testing capabilities in Penang, “due to increasing worldwide demand for Intel Foundry’s packaging offerings.”
Assembly Center
Chandrasekaran, who assumed leadership of Intel’s Foundry operations in 2025 and provided an exclusive interview to WIRED while this article was being researched, noted that the phrase “advanced packaging” was non-existent merely ten years prior.
Semiconductors have consistently necessitated a form of integrating transistors and capacitors, components that regulate and retain energy. For an extended period, the chip manufacturing sector concentrated on miniaturization, specifically, reducing the dimensions of chip constituents. With global expectations for computing power rising throughout the 2010s, chips progressively became more compact, incorporating processing units, high-bandwidth memory, and all vital interconnecting elements. Ultimately, semiconductor producers began adopting a system-in-packages or package-on-package methodology, where numerous constituents were layered sequentially to extract enhanced power and memory from an identical surface area. Two-dimensional layering evolved into three-dimensional layering.
TSMC, globally recognized as the foremost semiconductor producer, started presenting packaging innovations such as CoWoS (chip on wafer on substrate) and, subsequently, SoIC (system on integrated chip) to its clientele. Fundamentally, their proposal was that TSMC would manage not only the initial stages of chip fabrication—the wafer segment—but also the concluding stages, where all the chip’s technological elements would be assembled.
At this juncture, Intel had relinquished its primary position in chip fabrication to TSMC, yet persisted in channeling resources into packaging. In 2017, it launched a technique named EMIB, or embedded multi-die interconnect bridge, notable for its ability to reduce the physical connections, or bridges, among the elements within the chip package. Two years later, in 2019, Foveros, a sophisticated die-stacking procedure, was unveiled. The subsequent packaging breakthrough from the corporation represented a more substantial progression: EMIB-T.
Revealed in May of the previous year, EMIB-T pledges to enhance power effectiveness and signal coherence across all chip constituents. A past Intel staff member, possessing firsthand insight into the firm’s packaging initiatives, informed WIRED that Intel’s EMIB and EMIB-T are intended as a more “precise” method for chip packaging compared to TSMC’s methodology. Similar to a majority of chip innovations, this is anticipated to boost power efficiency, conserve physical area, and, optimally, reduce expenses for consumers over time. The corporation asserts EMIB-T will be deployed in fabrication plants this current year.
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